Adders, multipliers, etc., are logical elements that perform basic and extended digital numerical operations in digital processors such as microprocessors, digital signal processors (“DSPs”), arithmetic logic units (“ALUs”), hardware accelerators (HACs”), etc. Extended operations include square root, division, etc., which can require substantial numerical processing, inherently increase their complexity. The overall performance of digital processors is generally dependent on the speed and energy efficiency of its constituent logical elements.
The design of adders, multipliers, etc., is heavily dependent on the format representation of the numbers on which they operate. The cost of microprocessors, DSPs, etc., is substantially proportional to the silicon area required to implement the logical elements from which they are formed. An important consideration in providing a competitive design for an end product is improvement in speed required for execution of numerical operations. The floating-point representation of numbers employed therein can have a substantial impact on the speed of numerical operations and the silicon area required for an implementation.
Thus, what is needed in the art is a floating-point number representation that avoids numerical processing inefficiencies encountered in present implementations. The ability to improve the performance and reduce the silicon area required to implement DSPs, HACs, etc., without incurring unnecessary cost would answer an important market need.